Pll using unbalanced quadricorrelator

ABSTRACT

A Phase Locked Loop ( 1 ) used in a data and clock recovery comprising a frequency detector ( 10 ) including a quadricorrelator ( 2 ), the quadricorrelator ( 2 ) comprising a frequency detector including double edge clocked bi-stable circuits ( 21, 22, 23, 24 ) coupled to a first multiplexer ( 31 ) and to a second multiplexer ( 32 ) being controlled by a signal having a same bitrate as the incoming signal (D), and a phase detector (DFF) controlled by a first signal pair (PQ, {overscore (PQ)} provided by the first multiplexer ( 31 ) and by a second signal pair (PI, {overscore (PI)}) provided by the second multiplexer ( 32 ).

The invention relates to a Phase Locked Loop (PLL) comprising afrequency detector including an unbalanced quadricorrelator.

PLL circuits are widely used in modern communication circuits for tuningreceivers. Normally a PLL comprises a voltage-controlled oscillator(VCO), a frequency control loop having a frequency detector and a phasecontrol loop including a phase detector. When the incoming signal in thePLL is a high-speed Non Return to Zero (NRZ) random signal, phasedetectors and frequency detectors have the difficult task to work onrandom transitions of the incoming signal. PLLs using NRZ signals areoften called data and clock recovery circuits (ICR). Between transitionsthe phase and frequency detectors should maintain the phase error andfrequency error information such that the voltage controlled oscillatoris not pulled away from lock when transitions are missing.

A known implementation of the frequency detector is the quadricorrelatorconcept as in “Digital Logic Implementation of Quadricorrelators forFrequency detectors”, by C. G. Yoon, S. Y. Lee and C. W. Lee, IEEE Proc.of 37^(th) MidWest Symposium on Circuits and Systems, 1994, pp. 757-760.A model for an unbalanced digital quadricorrelator is an unbalancedanalog quadricorrelator as shown in FIG. 1. The analog quadricorrelatorcomprises a first pair of mixers M1, M2 supplied by quadrature signalsI, Q and input signal INP. Outputs of said pair of mixers M1, M2 arecoupled to a pair of low-pass filters L1, L2, the filters providingsignals Vi and Vq, respectively. The signal Vi is inputted to aderivation circuit D1. The signal Vq and the signal provided by thederivation circuit D1 are inputted to a third mixer M3, the mixergenerating a signal FD, which is indicative for a frequency errorbetween the input signal INP and quadrature signals I, Q. In theabove-mentioned document a digital implementation of the analog balancedquadricorrelator, is presented. The digital implementation comprisessingle edge flip-flops coupled to a combinatorial network Hence, theflip-flops detects only phase shifts between quadrature inputs and arising edge of the D input signal, which means that thisquadricorrelator works at half rate or 2* Tbit. Tbit is defined as thetime period for a high or a low binary level. Furthermore, thecombinatorial part of the quadricorrelator comprises 6 AND gates and 2OR gates that cause delays or, alternately, phase-shifts between thesignals provided by the quadricorrelator.

It is therefore an object of this invention to mitigate at least some ofthe above mentioned problems.

In accordance with the invention this is achieved in a device asdescribed in the first paragraph being characterized in that thequadricorrelator comprises a frequency detector including double edgeclocked bi-stable circuits coupled to a first multiplexer and to asecond multiplexer being controlled by a signal having a same bitrate asthe incoming signal, and a phase detector controlled by a first signalpair provided by the first multiplexer and by a second signal pairprovided by the second multiplexer. According to the invention, theinput information is read on both the rising and falling edges of theclock signal, meaning that the input information is read every halfperiod of the clock i.e. at Tbit rate. This feature could be implementedeither having a direct coupling between the clock signal and bi-stablecircuits or using intermediate signals obtained during processing inputsignal having the same Tbit. This means that bi-stable circuits could becombined with combinatorial circuits having a control input e.g.multiplexers for working at Tbit speed. Furthermore, the phase detectorcomprises a double edge bi-stable circuit and therefore it preserves theTbit speed. It is further observed that a delay of a signal through onebi-stable circuit is expected to be less that a delay through threelayers of combinatorial circuits as used in the prior-art.

In an embodiment of the invention the frequency detector comprises afirst pair of double edge clocked bi-stable circuits coupled to thefirst multiplexer and a second pair of double edge clocked bi-stablecircuits coupled to the second multiplexer, which first and second pairsare supplied by mutually quadrature phase shifted signals, respectively,to provide the first signal pair and the second signal pair indicativefor a phase difference between the incoming signal and mutuallyquadrature phase shifted signals. The first multiplexer and the secondmultiplexer provide a first signal and a second signal indicative for aphase difference between the incoming signal and mutually quadraturephase shifted signals. The mutually quadrature phase shifted signals aregenerated by a voltage controlled oscillator. In many applications asoptical networking a clock recovery is necessary especially when theclock information in missing from the input signal as in Non Return toZero (NRZ) signals. Furthermore, clock recovery circuits, which are infact PLLs having a quadrature voltage-controlled oscillator providingquadrature signals i.e. mutually shifted with 45 degrees. PLLs also havea phase detector and a frequency detector. The outputs of themultiplexers are updated only on the transitions of the incoming signalmaintaining the same error at the output between transitions. The phasedifference between the incoming signal and quadrature clock signals istransformed in a positive or negative quantified signal. When thissignal is positive the clock increases its phase and for negativesignals, the clock decreases its phase.

In another embodiment of the invention the phase detector comprises a Dflip-flop receiving the first signal pair and being clocked by thesecond signal pair, the second signal pair being inputted to respectivegates of a first transistor pair for determining a state ON or OFF of acurrent through said first transistor pair. The current through thefirst transistor pair biases a second transistor pair, the secondtransistors pair receiving the first signal pair and generating anoutput signal indicative for a frequency error between the incoming datasignal and Clock signals. According to the second signals pair, thecurrent can flow in the source of the first transistors or can be dumpedto Vcc. In equilibrium, a differential output of the frequency detectoris zero.

The above and other features and advantages of the invention will beapparent from the following description of the exemplary embodiments ofthe invention with reference to the accompanying drawings, in which:

FIG. 1 depicts a prior art quadricorrelator,

FIG. 2 depicts a schematic diagram of digital quadricorrelator accordingto the invention,

FIG. 3 depicts rotating wheel analogy for mutually quadrature signals,

FIG. 4 depicts frequency detection algorithm, according to theinvention, and

FIG. 5 depicts a PLL having a frequency detector as described in thepresent invention.

FIG. 2 depicts a schematic diagram of digital quadricorrelator accordingto the invention. The quadricorrelator 2 comprises double edge clockedbi-stable circuits 21, 22, 23, 24 coupled to multiplexers 31, 32 beingcontrolled by a signal having the same bit rate as the incoming signalD. A first pair of double edge clocked bi-stable circuits 21, 22 coupledto a first multiplexer 31 and a second pair of double edge clockedbi-stable circuits 23, 24 coupled to a second multiplexer 32 aresupplied by mutually quadrature phase shifted signals CKQ and CKIrespectively and providing a first pair of signals PQ, {overscore (PQ)}and a second pair of signals PI, {overscore (PI)} indicative for a phasedifference between the incoming signal D and mutually quadrature phaseshifted signals CKQ, CKI. It could be pointed out here that thebi-stable circuits could be flip-flops or latches. For the purpose ofillustration in FIG. 2 is shown an implementation using D-type latches.The mutually quadrature signals are generated by a voltage controlledoscillator VCO, shown in FIG. 5.

The combination latch-multiplexer performs as a latch clocked on bothtransitions of the incoming signal D. The incoming signal D transitionsare sampled by the two quadrature signals CKQ and CKI at Tbit rate. Theoutputs of the multiplexers are updated only on the incoming signal Dtransitions keeping the same error at the output between transitions.The second signal pair PI, {overscore (PI)} is the output of the phasedetector and the first pair of signals PQ, {overscore (PQ)} is inquadrature with it. The phase difference between the incoming signal Dand CKQ, respectively CKI is transformed in a positive or negativequantified signal. When this signal is positive the clock increases itsphase and for negative signals, the clock decreases its phase. Letdenote the first pair of signals PQ, {overscore (PQ)} as Q and thesecond pair of signals PI, {overscore (PI)} as L and let us furtherobserve that the signals I and Q are differential signals i.e. they aremutually shifted by substantially 180 degrees. The phase detectorcomprises a D flip-flop DFF receiving the first signal pair Q and beingclocked by the second signal pair I. The second signals pair I isinputted to a first transistor pair T1, T2 respective gates fordetermining a state ON or OFF of a current IO through said firsttransistors pair T1, T2. The current IO is generated by a current sourcecoupled to a common source node of the transistors T1, T2. The currentIO through the first transistor pair T1, T2 biases a second transistorpair T3, T4, the second transistor pair T3, T4 receiving the firstsignal pair Q and generating an output signal FD+, FD− indicative for afrequency error between the incoming data signal D and Clock signalsCKI, CKQ. Let us denote the output signal FD+, FD− as FD. The algorithmcan be visualized as shown in FIG. 4. Obviously the four possible caseswill converge towards the equilibrium position. Table 1 presents thefour situations and can be used to build the logic for the frequencydetector.

As shown in FIG. 2, the second signal I is used to clock the D latchDFF, sampling the first signal Q. According to the I values, the currentIo can flow in the source of the first transistor pair T1, T2 or can bedumped to Vcc. In equilibrium, when I is positive the first transistorpair T1, T2 is not active any longer and the differential output FD ofthe frequency detector is zero. Now, only the phase detector contributesto the phase correction. TABLE 1 Frequency detector logic PD_I (Ivector) PD_Q (Q vector) FD −/+ −1 0 −/+ 1 0 +/− −1 −1 +/− 1 +1

The equilibrium position for the signals I and Q can be represented withthe rotating wheel analogy as shown in FIG. 3. When it is a phase lock,the vector I is positive, stable and equal with +1 and the Q vectorbounces from the positive to the negative quadrant in a periodicfashion. Frequency error generation signal for the frequency detector isexplained with the aid of FIG. 4 and comprises the following steps:

-   -   When I has a negative to positive transition for positive Q        vectors, keep the frequency by generating a zero signal at the        output of the frequency detector.    -   When I has a negative to positive transition for negative Q        vectors, keep the frequency by generating a zero signal at the        output of the frequency detector.

When I has a positive to negative transition and Q is positive, increasethe frequency (FD=+1)

-   -   When I has a positive to negative transition and Q is negative,        decrease the frequency (FD=−1).

When the clock is too slow as shown in FIG. 4, the pair of the twoquadrature signals I and Q rotate counter-clockwise with an angularfrequency equal to the frequency difference Δω and the derivative of thesignal I failing on top of Q signal generating an error signal.

When the clock is too fast, the pair of the two quadrature signals I andQ rotate clockwise with an angular frequency equal to the frequencydifference Δω and the derivative of the signal I falling in top ofsignal Q with 180° phase difference signal generating an error signal.

FIG. 5 depicts a PLL having a frequency detector 10 as described in thepresent invention. The error signal FD is inputted to a coarse controlinput C of the voltage controlled oscillator VCO via a first charge pump20 coupled to a first low-pass filter 30 coupled to a second adder 80.The frequency error signal FD is inputted to the coarse input C of theVCO because the VCO has to adapt as quickly as possible to frequencydifferences between the incoming signal D and the quadrature signals CKIand CKQ. A fine control input F of the VCO is controlled by a signal PDprovided by a phase detector 70 coupled to a second charge pump 60coupled to second low-pass filter 50.

Once the frequency lock is acquired the output of the frequency detectorprovides a zero DC signal at the output such that the VCO keeps thefrequency information.

It is remarked that the scope of protection of the invention is notrestricted to the embodiments described herein. Neither is the scope ofprotection of the invention restricted by the reference numerals in theclaims. The word ‘comprising’ does not exclude other parts than thosementioned in the claims. The word ‘a(n)’ preceding an element does notexclude a plurality of those elements. Means forming part of theinvention may both be implemented in the form of dedicated hardware orin the form of a programmed purpose processor. The invention resides ineach new feature or combination of features. Throughout the descriptionit was assumed that the signals L Q and F are binary signals having anON state represented by a +1 value and an OFF state represented by a −1value.

1. A Phase Locked Loop comprising a frequency detector including anunbalanced quadricorrelator, the quadricorrelator comprising a frequencydetector including double edge clocked bi-stable circuits coupled to afirst multiplexer and to a second multiplexer being controlled by asignal having a same bitrate as the incoming signal, and a phasedetector controlled by a first signal pair provided by the firstmultiplexer and by a second signal pair provided by the secondmultiplexer.
 2. A Phase Locked Loop as claimed in claim 1, wherein thefrequency detector comprises a first pair of double edge clockedbi-stable circuits coupled to the first multiplexer, and a second pairof double edge clocked bi-stable circuits coupled to the secondmultiplexer, which first and second pairs are supplied by mutuallyquadrature phase shifted signals respectively to provide the firstsignal pair and the second signal pair indicative for a phase differencebetween the incoming signal and mutually quadrature phase shiftedsignals.
 3. A Phase Locked Loop as claimed in claim 1, wherein the phasedetector comprises a D flip-flop receiving the first signal pair andbeing clocked by the second signal pair, the second signal pair beinginputted to respective gates of a first transistors pair for determininga state ON or OFF of a current through said first transistors pair.
 4. APhase Locked Loop as claimed in claim 3, wherein current through thefirst transistor pair biases a second transistor pair, the secondtransistor pair receiving the first signal pair and generating an outputsignal indicative for a frequency error between the incoming data signaland Clock signals.
 5. A Phase Locked Loop as claimed in claim 2, whereinthe mutually quadrature phase shifted signals are generated by a voltagecontrolled oscillator.
 6. A Phase Locked Loop as claimed in 5, whereinthe error signal is inputted to a coarse control input of the voltagecontrolled oscillator via a first charge pump coupled to a firstlow-pass filter coupled to an adder.
 7. A Phase Locked Loop as claimedin claim 6, wherein a fine control input is controlled by a signalprovided by a phase detector coupled to a second charge pump coupled tosecond low-pass filter.